Florian Krieger

About Me:

Hi, I'm Florian and I am a PhD candidate at the Institute of Information Security at Graz University of Technology. I am part of the Cryptographic Engineering Group under the supervision of Prof. Sujoy Sinha Roy. My research focuses on efficient and secure implementations of Homomorphic Encryption and Zero-Knowledge Proof systems.

Interests

Hardware Acceleration
Software Implementations
Side-Channel Security

Teaching

Education

PhD in Computer Science, since 2024
Graz University of Technology
MSc in Information and Computer Engineering, 2023
Graz University of Technology
BSc in Information and Computer Engineering, 2022
Graz University of Technology

Publications

2026

Privacy at your Fingertips: Enabling Rapid Client-Side Operations in Fully Homomorphic Encryption
Aikata Aikata, Florian Krieger, Sujoy Sinha Roy
IEEE European Symposium on Security and Privacy (EuroS&P) 2026
Abstract BibTex Website

@misc{cryptoeprint:2026/515,
      author = {Aikata Aikata and Florian Krieger and Sujoy Sinha Roy},
      title = {Privacy at your Fingertips: Enabling Rapid Client-Side Operations in Fully Homomorphic Encryption},
      howpublished = {Cryptology {ePrint} Archive, Paper 2026/515},
      year = {2026},
      url = {https://eprint.iacr.org/2026/515}
}

High-Performance SIMD Software for Spielman Codes in Zero-Knowledge Proofs
Florian Krieger, Christian Dobrouschek, Florian Hirner, Sujoy Sinha Roy
Conference on Cryptographic Hardware and Embedded Systems (CHES) 2026
Abstract BibTex Website GitHub

@misc{cryptoeprint:2025/2301,
      author = {Florian Krieger and Christian Dobrouschek and Florian Hirner and Sujoy Sinha Roy},
      title = {High-Performance {SIMD} Software for Spielman Codes in Zero-Knowledge Proofs},
      howpublished = {Cryptology {ePrint} Archive, Paper 2025/2301},
      year = {2025},
      url = {https://eprint.iacr.org/2025/2301}
}

2025

A Flexible Hardware Design Tool for Fast Fourier and Number-Theoretic Transformation Architectures
Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Abstract BibTex Website GitHub

@article{11112724,
  author={Krieger, Florian and Hirner, Florian and Mert, Ahmet Can and Roy, Sujoy Sinha},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, 
  title={A Flexible Hardware Design Tool for Fast Fourier and Number-Theoretic Transformation Architectures}, 
  year={2025},
  volume={},
  number={},
  pages={1-13},
  keywords={Polynomials;Hardware;Fast Fourier transforms;Memory management;Cryptography;Read only memory;Optimization;Design tools;System-on-chip;Arithmetic;Hardware Design Tool;NTT;FFT;Twiddle Factor Generation;Fully Homomorphic Encryption (FHE)},
  doi={10.1109/TCAD.2025.3595834}}

Accelerating Hash-Based Polynomial Commitment Schemes with Linear Prover Time
Florian Hirner*, Florian Krieger*, Constantin Piber, Sujoy Sinha Roy (*shared first-authorship)
Conference on Cryptographic Hardware and Embedded Systems (CHES) 2025
Abstract BibTex Website GitHub

Zero-knowledge proofs (ZKPs) are cryptographic protocols that enable one party to prove the validity of a statement without revealing any information beyond its truth. Central building blocks in many ZKPs are polynomial commitment schemes (PCS) where constructions with linear-time provers are especially attractive. Two such examples are Brakedown and its extension Orion, which enable linear-time and quantum-resistant proving by leveraging linear-time encodable Spielman codes. However, these PCS operate over large datasets, creating significant computational bottlenecks. For example, committing to and proving a degree 2^28 polynomial requires around 1.1 GB of data while taking 463 seconds on a high-end server CPU. This work addresses the performance bottleneck in Orion-like PCS by optimizing their most critical operations: Spielman encoding and Merkle commitments. These operations involve Gigabytes of data and suffer from random off-chip memory access patterns that drastically reduce off-chip bandwidth. We resolve this issue and introduce inverted expander graphs to eliminate random writes and reduce off-chip memory accesses by over 50%. Additionally, we propose an on-the-fly graph sampling method that avoids streaming large auxiliary data by generating expander graphs dynamically on-chip. We also provide a formal security proof for our proposed graph transformation. Beyond encoding, we accelerate Merkle Tree construction over large data sets through a scalable multi-pass SHA3 pipeline. Finally, we reutilize existing hardware components used in commitment to accelerate the so-called proximity and consistency checks during proof generation. Building upon these concepts, we present the first hardware architecture for PCS - with linear prover time - on an Xilinx Alveo U280 FPGA. In addition, we discuss the practical challenges of manually partitioning, placing, and routing our large-scale architecture to efficiently map it to the multi-SLR and HBM-equipped FPGA. The final implementation achieves a speedup of two orders of magnitude for full proof generation, covering commitment and proving steps. When combined with Virgo as an outer CP-SNARK protocol, our accelerator reduces end-to-end latency by up to 3.85x - close to the theoretical maximum of 3.9x.

@article{Hirner_Krieger_Piber_Sinha Roy_2025, 
  title={Accelerating Hash-Based Polynomial Commitment Schemes with Linear Prover Time}, 
  volume={2025}, 
  url={https://tches.iacr.org/index.php/TCHES/article/view/12413}, 
  DOI={10.46586/tches.v2025.i4.341-385}, 
  number={4},
  journal={IACR Transactions on Cryptographic Hardware and Embedded Systems}, 
  author={Hirner, Florian and Krieger, Florian and Piber, Constantin and Sinha Roy, Sujoy}, 
  year={2025}, 
  month={Sep.}, 
  pages={341-385}}

Exploring Large Integer Multiplication for Cryptography Targeting In-Memory Computing
Florian Krieger, Florian Hirner, Sujoy Sinha Roy
Design, Automation & Test in Europe Conference (DATE) 2025
Abstract BibTex Website Poster Slides

@inproceedings{10992977,
  author={Krieger, Florian and Hirner, Florian and Roy, Sujoy Sinha},
  booktitle={2025 Design, Automation & Test in Europe Conference (DATE)}, 
  title={Exploring Large Integer Multiplication for Cryptography Targeting In-Memory Computing}, 
  year={2025},
  volume={},
  number={},
  pages={1-7},
  keywords={Energy consumption;Pipelines;Europe;Throughput;In-memory computing;Common Information Model (computing);Software;Hardware;Cryptography;Homomorphic encryption;Computing In Memory;Large Integer Multiplication;Karatuba Multiplication},
  doi={10.23919/DATE64628.2025.10992977}}

Chiplet-Based Techniques for Scalable and Memory-Aware Multi-Scalar Multiplication
Florian Hirner, Florian Krieger, Sujoy Sinha Roy
Cryptology ePrint Archive (Preprint)
Abstract BibTex Website

@misc{cryptoeprint:2025/252,
  author = {Florian Hirner and Florian Krieger and Sujoy Sinha Roy},
  title = {Chiplet-Based Techniques for Scalable and Memory-Aware Multi-Scalar Multiplication},
  howpublished = {Cryptology {ePrint} Archive, Paper 2025/252},
  year = {2025},
  url = {https://eprint.iacr.org/2025/252}}

2024

Whipping the Multivariate-based MAYO Signature Scheme using Hardware Platforms
Florian Hirner, Michael Streibl, Florian Krieger, Ahmet Can Mert, Sujoy Sinha Roy
ACM SIGSAC Conference on Computer and Communications Security (CCS) 2024
Abstract BibTex Website Zenodo

NIST issued a new call in 2023 to diversify the portfolio of quantum- resistant digital signature schemes since the current portfolio relies on lattice problems. The MAYO scheme, which builds on the Un- balanced Oil and Vinegar (UOV) problem, is a promising candidate for this new call. MAYO introduces emulsifier maps and a novel 'whipping' technique to significantly reduce the key sizes compared to previous UOV schemes. This paper provides a comprehensive analysis of the implementation aspects of MAYO and proposes sev- eral optimization techniques that we use to implement a high-speed hardware accelerator. The first optimization technique is the partial unrolling of the emulsification process to increase parallelization. The second proposed optimization is a novel memory structure enabling the parallelization of significant bottlenecks in the MAYO scheme. In addition to this, we present a flexible transposing technique for the data format used in MAYO that can be expanded to other UOV-based schemes. We use these techniques to design the first high-speed ASIC and FPGA accelerator that supports all operations of the MAYO scheme for different NIST security levels. Compared with state-of-the-art, like HaMAYO and UOV, our FPGA design shows a performance benefit of up to three orders of magnitude in both latency and area-time-product. Furthermore, we lower the BRAM consumption by up to 2.8x compared to these FPGA implementations. Compared to high-end CPU implementa- tions, our ASIC design allows between 2.81x and 60.14x higher throughputs. This increases the number of signing operations per second from 483 to 13424, thereby fostering performant deployment of the MAYO scheme in time-critical applications.

@inproceedings{10.1145/3658644.3690258,
  author = {Hirner, Florian and Streibl, Michael and Krieger, Florian and Mert, Ahmet Can and Roy, Sujoy Sinha},
  title = {Whipping the Multivariate-based MAYO Signature Scheme using Hardware Platforms},
  year = {2024},
  isbn = {9798400706363},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  url = {https://doi.org/10.1145/3658644.3690258},
  doi = {10.1145/3658644.3690258},
  booktitle = {Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security},
  pages = {3421-3435},
  numpages = {15},
  keywords = {asic, digital signature, fpga, mayo, post-quantum},
  location = {Salt Lake City, UT, USA},
  series = {CCS '24}}

OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE
Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2024
Abstract BibTex Website GitHub Slides

@inproceedings{10.1145/3676536.3697123,
  author = {Krieger, Florian and Hirner, Florian and Mert, Ahmet Can and Sinha Roy, Sujoy},
  title = {OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE},
  year = {2025},
  isbn = {9798400710773},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  url = {https://doi.org/10.1145/3676536.3697123},
  doi = {10.1145/3676536.3697123},
  booktitle = {Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design},
  articleno = {13},
  numpages = {9},
  keywords = {hardware design tool, NTT, twiddle factor generation, FHE},
  location = {Newark Liberty International Airport Marriott, New York, NY, USA},
  series = {ICCAD '24}}

Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption
Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
Design, Automation & Test in Europe Conference & Exhibition (DATE) 2024
Abstract BibTex Website GitHub Poster Slides

@inproceedings{10546608,
  author={Krieger, Florian and Hirner, Florian and Mert, Ahmet Can and Roy, Sujoy Sinha},
  booktitle={2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, 
  title={Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption}, 
  year={2024},
  volume={},
  number={},
  pages={1-6},
  keywords={Cloud computing;Design methodology;Seals;Computer architecture;Encoding;Resource management;Homomorphic encryption;CKKS;Homomorphic Encryption;Hardware Accelerator;FPGA;Microsoft SEAL},
  doi={10.23919/DATE58400.2024.10546608}}

Talks

2025

OpenNTT: An Automated Toolchain for Compiling High-Performance NTT and FFT Accelerators
Florian Krieger
OPTIMIST Workshop 2025
Slides

Accelerating Hash-Based Polynomial Commitment Schemes with Linear Prover Time
Florian Hirner and Florian Krieger
IACR Conference on Cryptographic Hardware and Embedded Systems (CHES) 2025
Slides

Exploring Large Integer Multiplication for Cryptography Targeting In-Memory Computing
Florian Krieger
Design, Automation & Test in Europe Conference (DATE) 2025
Poster Slides

2024

OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE
Florian Krieger
IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2024
Slides

AMD Open Hardware Compretition: Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption
Florian Krieger
AMD Open Hardware Design Competition 2024
Info Recording

Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption
Florian Krieger
Design, Automation & Test in Europe Conference (DATE) 2024
Poster Slides

Open-Source Artifacts

2026

High-Performance SIMD Software for Spielman Codes in Zero-Knowledge Proofs
AVX512-IFMA implementation of the Spielman encoding in Brakedown and related proof systems.

2025

OpenNTT
A hardware generation tool for compiling high-performance NTT and FFT accelerators.

Hardware Accelerator for the Orion Polynomial Commitment Scheme
We targeted a high-end Alveo U280 datacenter FPGA with HBM and DDR interfaces for this work.

2024

Aloha-HE: Extended for the AMD Open Hardware Competition
Info

Aloha-HE
An open-source hardware accelerator for client-side FHE.

Awards

2024

Award of Distinction - Federal Prize for the Best Diploma and Master's Degrees
Federal Ministry for Education, Science and Research, Austria

ISEC Student Research Excellence Award for Aloha-HE
Institute of Information Security, Graz University of Technology

Finalist in the AMD Open Hardware Design Competiton
AMD

WKO Research Grant for Outstanding Master Theses with High Industrial Relevance
Economic Chamber Styria